The semiconductor industry has a market driven need to reduce the size of devices such as transistors, and to thus increase the operational speed of the device as well as reduce the device power consumption. To reduce transistor size, the thickness of the silicon dioxide, SiO2, gate dielectric is reduced in proportion to the shrinkage of the gate length. For example, a metal-oxide-semiconductor field effect transistor (MOSFET) would use a 1.5 nm thick SiO2 gate dielectric for a gate length of less than 100 nm. This scaling of gate dielectric thickness may be the most difficult issue facing the production of the next generation of MOSFETs. These increasingly smaller, faster, lower power consumption and more reliable integrated circuits (ICs) will likely be used in manufacturing products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs).
Currently, the semiconductor industry reduces (or scales down) all of the dimensions of its basic devices, such as the silicon based MOSFET, to achieve the required improved operation. As mentioned, this device scaling includes scaling the gate dielectric, which has primarily been formed of silicon dioxide (SiO2). A thermally grown amorphous SiO2 layer provides a good electrically and thermodynamically stable material, where the interface of the SiO2 layer with underlying silicon provides a high quality interface as well as superior electrical isolation properties. However, continued scaling in microelectronic devices has created problems as the gate dielectric has become thinner, such as increased leakage currents passing through the gate dielectric. Thus there is a need to develop other dielectric materials for use as gate dielectrics, in particular dielectric materials with higher dielectric constants (k) than the relatively low k value of silicon dioxide.